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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 45
GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia
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UNIT 3
ANALOG CIRCUITS
2013 ONE MARK
3.1 In the circuit shown below what is the output voltage Vout^ h if a
silicon transistor Q and an ideal opamp are used?
(A) 15 V (B) 0.7 V
(C) 0.7 V+ (D) 15 V+
3.2 In a voltagevoltage feedback as shown below, which one of the
following statements is TRUE if the gain k is increased?
(A) The input impedance increases and output impedance decreas
es
(B) The input impedance increases and output impedance also
increases
(C) The input impedance decreases and output impedance also
decreases
(D) The input impedance decreases and output impedance increas
es
2013 TWO MARKS
3.3 In the circuit shown below, the knee current of the ideal Zener
dioide is 10 mA. To maintain 5 V across RL , the minimum value of
RL in W and the minimum power rating of the Zener diode in mW
, respectively, are
(A) 125 and 125 (B) 125 and 250
(C) 250 and 125 (D) 250 and 250
3.4 The ac schematic of an NMOS commonsource state is shown in the
figure below, where part of the biasing circuits has been omitted for
simplicity. For the n channel MOSFET M, the transconductance
1 /mA Vgm = , and body effect and channel length modulation effect
are to be neglected. The lower cutoff frequency in HZ of the circuit
is approximately at
(A) 8 (B) 32
(C) 50 (D) 200
3.5 In the circuit shown below the opamps are ideal. Then, Vout in Volts
is
(A) 4 (B) 6
(C) 8 (D) 10
3.6 In the circuit shown below, Q1 has negligible collectortoemitter
saturation voltage and the diode drops negligible voltage across it
under forward bias. If Vcc is 5 V+ , X and Y are digital signals with
0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is
(A) XY (B) XY
(C) XY (D) XY
3.7 A voltage sin t1000 w Volts is applied across YZ . Assuming ideal
diodes, the voltage measured across WX in Volts, is
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(A) sin tw (B) /sin sint t 2w w+_ i
(C) /sin sint t 2w w^ h (D) 0 for all t
3.8 In the circuit shown below, the silicon npn transistor Q has a
very high value of b . The required value of R2 in kW to produce
1 mAIC = is
(A) 20 (B) 30
(C) 40 (D) 50
2012 ONE MARK
3.9 The current ib through the base of a silicon npn transistor is
1 0.1 (1000 )cos mAt0p+ At 300 K, the rp in the small signal model
of the transistor is
(A) 250W (B) 27.5W
(C) 25W (D) 22.5W
3.10 The i v characteristics of the diode in the circuit given below are
i
. , .
.
A V
A V
v v
v
500
0 7 0 7
0 0 7<
$
=

*
The current in the circuit is
(A) 10 mA (B) 9.3 mA
(C) 6.67 mA (D) 6.2 mA
3.11 The diodes and capacitors in the circuit shown are ideal. The voltage
( )v t across the diode D1 is
(A) ( )cos t 1w  (B) ( )sin tw
(C) 1 ( )cos tw (D) ( )sin t1 w
3.12 The impedance looking into nodes 1 and 2 in the given circuit is
(A) 05 W (B) 100W
(C) 5 kW (D) 10.1 kW
2012 TWO MARKS
3.13 The circuit shown is a
(A) low pass filter with
( )
/rad sf
R R C
1
dB3
1 2
=
+
(B) high pass filter with /rad sf
R C
1
dB3
1
=
(C) low pass filter with /rad sf
R C
1
dB3
1
=
(D) high pass filter with
( )
/rad sf
R R C
1
dB3
1 2
=
+
3.14 The voltage gain Av of the circuit shown below is
(A) A 200v . (B) A 100v .
(C) A 20v . (D) A 10v .
2011 ONE MARK
3.15 In the circuit shown below, capacitors C1 and C2 are very large and
are shorts at the input frequency. vi is a small signal input. The gain
magnitude v
v
i
o at 10 M rad/s is
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1996 TWO MARKS
3.145 In the circuit shown in the given figure N is a finite gain amplifier
with a gain of k , a very large input impedance, and a very low
output impedance. The input impedance of the feedback amplifier
with the feedback impedance Z connected as shown will be
(A) Z
k
1 1b l (B) ( )Z k1 
(C)
( )k
Z
1
(D)
( )k
Z
1 
3.146 A Darlington stage is shown in the figure. If the transconductance of
Q1 is gm1 and Q2 is gm2, then the overall transconductance g v
i
mc
be
c
c
c
T; E
is given by
(A) gm1 (B) . g0 5 m1
(C) gm2 (D) . g0 5 m2
3.147 Value of R in the oscillator circuit shown in the given figure, so
chosen that it just oscillates at an angular frequency of w. The value
of w and the required value of R will respectively be
(A) 10 / , 2 10secrad5 4 W# (B) / , 2 10secrad2 104 4# W#
(C) 2 10 / ,10secrad4 5 W# (D) 10 / ,10secrad5 5 W
3.148 A zener diode in the circuit shown in the figure is has a knee current
of 5 mA, and a maximum allowed power dissipation of 300 mW
. What are the minimum and maximum load currents that can
be drawn safely from the circuit, keeping the output voltage V0
constant at 6 V?
(A) 0 , 180mA mA (B) 5 , 110mA mA
(C) 10 , 55mA mA (D) 60 ,180mA mA
***********
Page 17
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 61
GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia
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SOLUTIONS
3.1 Option (B) is correct.
For the given ideal opamp, negative terminal will be also ground
(at zero voltage) and so, the collector terminal of the BJT will be
at zero voltage.
i.e., VC 0 volt=
The current in 1 kW resistor is given by
I
1 k
5 0
W
=  5 mA=
This current will flow completely through the BJT since, no cur
rent will flow into the ideal opamp ( /I P resistance of ideal op
amp is infinity). So, for BJT we have
VC 0=
VB 0=
IC 5 mA=
i.e.,the base collector junction is reverse biased (zero voltage)
therefore, the collector current (IC ) can have a value only if base
emitter is forward biased. Hence,
VBE 0.7 volts=
& V VB E .0 7=
& V0 out .0 7=
or, Vout 0.7 volt=
3.2 Option (A) is correct.
The /i p voltage of the system is given as
Vin V Vf1= +
V kVout1= +
V k A V1 0 1= + V A Vout 0 1=^ h
V k A11 0= +^ h
Therefore, if k is increased then input voltage is also increased so,
the input impedance increases. Now, we have
Vout A V0 1=
A
k A
V
1
in
0
0
=
+^ h
k A
A V
1
in
0
0=
+^ h
Since, Vin is independent of k when seen from output mode, the
output voltage decreases with increase in k that leads to the decrease
of output impedance. Thus, input impedance increases and output
impedance decreases.
3.3 Option (B) is correct.
From the circuit, we have
Is I IZ L= +
or, IZ I Is L= 
(1)
Since, voltage across zener diode is 5 V so, current through 100W
resistor is obtained as
Is 0.05 A100
10 5=  =
Therefore, the load current is given by
IL R
5
L
=
Since, for proper operation, we must
have
IZ Iknes$
So, from Eq. (1), we write
0.05 A
R
5
L
 10 mA$
50 mA
R
5
L
 10 mA$
40 mA
R
5
L
$
40 10 3#

R
5
L
$
1
40 10 3#

R
5
L#
40 10
5
3
#
 RL#
or, 125W RL#
Therefore, minimum value of 125RL W=
Now, we know that power rating of Zener diode is given by
PR V I maxZ Z= ^ h
I maxZ^ h is maximum current through zener diode in reverse bias.
Maximum currrent through zener diode flows when load current is
zero. i.e.,
I maxZ^ h .I 100
10 5 0 05s= =
 =
Therefore, PR 5 0.05 W#=
250 mW=
3.4 Option (A) is correct.
For the given circuit, we obtain the small signal model as shown in
figure below :
We obtain the node voltage at V1 as
R
V
R
sC
V g V1D
L
m i
1 1+
+
+ 0=
& V1
R R
sC
g V
1
1
1
D
L
m i=
+
+

Therefore, the output voltage V0 is obtained as
V0
R
sC
V R
1
L
L1=
+
R
sC
R
R R
sC
g V
1 1
1
1
L
L
D
L
m i=
+ +
+
J
L
K
K
K
N
P
O
O
O
so, the transfer function is
V
V
i
0
sC R R
R R sCg
1 D L
D L m=
+ +

^ h
Then, we have the pole at
C R R
1
D L
w =
+^ h
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The equivalent circuit of given amplifier circuit (when CE is
connected, RE is shortcircuited)
Input impedance Ri R rB= p
Voltage gain AV g Rm C=
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance Rin  [ ( )]R r R1B Eb= + +p
Input impedance increases
Voltage gain AV g R
g R
1 m E
m C= + Voltage gain decreases.
3.138 Option (A) is correct.
In common emitter stage input impedance is high, so in cascaded
amplifier common emitter stage is followed by common base stage.
3.139 Option (C) is correct.
We know that collectemitter break down voltage is less than
compare to collector base breakdown voltage.
BVCEO BV< CBO
both avalanche and zener break down. Voltage are higher than
BVCEO.So BVCEO limits the power supply.
3.140 Option (C) is correct.
If we assume consider the diode in reverse bias then Vn should be
greater than VP .
V V<P n
by calculating
VP 4 5 Volt4 4
10
#= + =
Vn 2 1 2 Volt#= =
here V V>P n (so diode cannot be in reverse bias mode).
apply node equation at node a
V V V
4
10
4 1
a a a + + 2=
V6 10a 8=
Va 3 Volt=
so current Ib 4
0 3
4
10 3=  + 
Ib 1 amp4
10 6=  =
3.141 Option (D) is correct.
By applying node equation at terminal (2) and (3) of OP amp
V Q V V
5 10
a a 0 +  0=
V V V2 4a a 0 +  0=
V0 V3 4a= 
V V V100 10
0a a0 +  0=
V V V10a a0 + 0=
V11 a V0=
Va
V
11
0=
So V0
V
11
3 40= 
V11
8 0 4=
V0 5.5 Volts=
3.142 Option (B) is correct.
Circuit with diode forward resistance looks
So the DC current will
IDC ( )R R
V
f L
m
p
=
+
3.143 Option (D) is correct.
For the positive half cycle of input diode D1 will conduct & D2 will
be off. In negative half cycle of input D1 will be off & D2 conduct so
output voltage wave from across resistor (10 )kW is –
Ammeter will read rms value of current
so Irms ( )half wave rectifierR
Vm
p=
(10 )k
4
pW
= .0 4p= mA
3.144 Option (D) is correct.
In given circuit positive feedback is applied in the opamp., so it
works as a Schmitt trigger.
Page 33
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 77
GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia
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3.145 Option (D) is correct.
Gain with out feedback factor is given by
V0 kVi=
after connecting feedback impedance Z
given input impedance is very large, so after connecting Z we have
Ii Z
V Vi 0=  V kVi0 =
Ii Z
V kVi i= 
input impedance Zin ( )I
V
k
Z
1i
i= =

3.146 Option (A) is correct.
3.147 Option (A) is correct.
For the circuit, In balanced condition It will oscillated at a frequency
w
.
10 / secrad
LC
1
10 10 01 10
1
3 6
5
# # #
= = =
 
In this condition
R
R
2
1
R
R
4
3=
5100
R
1=
R 20 k 2 104#W W= =
3.148 Option (C) is correct.
V0 kept constant at V0 6 volt=
so current in 50W resistor
I
50
9 6
W
= 
I 60 m amp=
Maximum allowed power dissipation in zener
PZ 300 mW=
Maximum current allowed in zener
PZ ( )V I 300 10maxZ Z
3
#= = 
& ( )I6 300 10maxZ
3
#= = 
& ( ) 50 m ampI maxZ= =
Given knee current or minimum current in zener
( )I minZ 5 m amp=
In given circuit I I IZ L= +
IL I IZ= 
( )I minL ( )I I maxZ= 
(60 50)m amp m amp10=  =
( )I maxL ( )I I minZ= 
(60 5) 55 m amp=  =
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia Page 45
GATE GUIDE and GATE CLOUD by RK Kanodia & Ashish Murolia
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UNIT 3
ANALOG CIRCUITS
2013 ONE MARK
3.1 In the circuit shown below what is the output voltage Vout^ h if a
silicon transistor Q and an ideal opamp are used?
(A) 15 V (B) 0.7 V
(C) 0.7 V+ (D) 15 V+
3.2 In a voltagevoltage feedback as shown below, which one of the
following statements is TRUE if the gain k is increased?
(A) The input impedance increases and output impedance decreas
es
(B) The input impedance increases and output impedance also
increases
(C) The input impedance decreases and output impedance also
decreases
(D) The input impedance decreases and output impedance increas
es
2013 TWO MARKS
3.3 In the circuit shown below, the knee current of the ideal Zener
dioide is 10 mA. To maintain 5 V across RL , the minimum value of
RL in W and the minimum power rating of the Zener diode in mW
, respectively, are
(A) 125 and 125 (B) 125 and 250
(C) 250 and 125 (D) 250 and 250
3.4 The ac schematic of an NMOS commonsource state is shown in the
figure below, where part of the biasing circuits has been omitted for
simplicity. For the n channel MOSFET M, the transconductance
1 /mA Vgm = , and body effect and channel length modulation effect
are to be neglected. The lower cutoff frequency in HZ of the circuit
is approximately at
(A) 8 (B) 32
(C) 50 (D) 200
3.5 In the circuit shown below the opamps are ideal. Then, Vout in Volts
is
(A) 4 (B) 6
(C) 8 (D) 10
3.6 In the circuit shown below, Q1 has negligible collectortoemitter
saturation voltage and the diode drops negligible voltage across it
under forward bias. If Vcc is 5 V+ , X and Y are digital signals with
0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is
(A) XY (B) XY
(C) XY (D) XY
3.7 A voltage sin t1000 w Volts is applied across YZ . Assuming ideal
diodes, the voltage measured across WX in Volts, is
Page 2
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(A) sin tw (B) /sin sint t 2w w+_ i
(C) /sin sint t 2w w^ h (D) 0 for all t
3.8 In the circuit shown below, the silicon npn transistor Q has a
very high value of b . The required value of R2 in kW to produce
1 mAIC = is
(A) 20 (B) 30
(C) 40 (D) 50
2012 ONE MARK
3.9 The current ib through the base of a silicon npn transistor is
1 0.1 (1000 )cos mAt0p+ At 300 K, the rp in the small signal model
of the transistor is
(A) 250W (B) 27.5W
(C) 25W (D) 22.5W
3.10 The i v characteristics of the diode in the circuit given below are
i
. , .
.
A V
A V
v v
v
500
0 7 0 7
0 0 7<
$
=

*
The current in the circuit is
(A) 10 mA (B) 9.3 mA
(C) 6.67 mA (D) 6.2 mA
3.11 The diodes and capacitors in the circuit shown are ideal. The voltage
( )v t across the diode D1 is
(A) ( )cos t 1w  (B) ( )sin tw
(C) 1 ( )cos tw (D) ( )sin t1 w
3.12 The impedance looking into nodes 1 and 2 in the given circuit is
(A) 05 W (B) 100W
(C) 5 kW (D) 10.1 kW
2012 TWO MARKS
3.13 The circuit shown is a
(A) low pass filter with
( )
/rad sf
R R C
1
dB3
1 2
=
+
(B) high pass filter with /rad sf
R C
1
dB3
1
=
(C) low pass filter with /rad sf
R C
1
dB3
1
=
(D) high pass filter with
( )
/rad sf
R R C
1
dB3
1 2
=
+
3.14 The voltage gain Av of the circuit shown below is
(A) A 200v . (B) A 100v .
(C) A 20v . (D) A 10v .
2011 ONE MARK
3.15 In the circuit shown below, capacitors C1 and C2 are very large and
are shorts at the input frequency. vi is a small signal input. The gain
magnitude v
v
i
o at 10 M rad/s is
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1996 TWO MARKS
3.145 In the circuit shown in the given figure N is a finite gain amplifier
with a gain of k , a very large input impedance, and a very low
output impedance. The input impedance of the feedback amplifier
with the feedback impedance Z connected as shown will be
(A) Z
k
1 1b l (B) ( )Z k1 
(C)
( )k
Z
1
(D)
( )k
Z
1 
3.146 A Darlington stage is shown in the figure. If the transconductance of
Q1 is gm1 and Q2 is gm2, then the overall transconductance g v
i
mc
be
c
c
c
T; E
is given by
(A) gm1 (B) . g0 5 m1
(C) gm2 (D) . g0 5 m2
3.147 Value of R in the oscillator circuit shown in the given figure, so
chosen that it just oscillates at an angular frequency of w. The value
of w and the required value of R will respectively be
(A) 10 / , 2 10secrad5 4 W# (B) / , 2 10secrad2 104 4# W#
(C) 2 10 / ,10secrad4 5 W# (D) 10 / ,10secrad5 5 W
3.148 A zener diode in the circuit shown in the figure is has a knee current
of 5 mA, and a maximum allowed power dissipation of 300 mW
. What are the minimum and maximum load currents that can
be drawn safely from the circuit, keeping the output voltage V0
constant at 6 V?
(A) 0 , 180mA mA (B) 5 , 110mA mA
(C) 10 , 55mA mA (D) 60 ,180mA mA
***********
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SOLUTIONS
3.1 Option (B) is correct.
For the given ideal opamp, negative terminal will be also ground
(at zero voltage) and so, the collector terminal of the BJT will be
at zero voltage.
i.e., VC 0 volt=
The current in 1 kW resistor is given by
I
1 k
5 0
W
=  5 mA=
This current will flow completely through the BJT since, no cur
rent will flow into the ideal opamp ( /I P resistance of ideal op
amp is infinity). So, for BJT we have
VC 0=
VB 0=
IC 5 mA=
i.e.,the base collector junction is reverse biased (zero voltage)
therefore, the collector current (IC ) can have a value only if base
emitter is forward biased. Hence,
VBE 0.7 volts=
& V VB E .0 7=
& V0 out .0 7=
or, Vout 0.7 volt=
3.2 Option (A) is correct.
The /i p voltage of the system is given as
Vin V Vf1= +
V kVout1= +
V k A V1 0 1= + V A Vout 0 1=^ h
V k A11 0= +^ h
Therefore, if k is increased then input voltage is also increased so,
the input impedance increases. Now, we have
Vout A V0 1=
A
k A
V
1
in
0
0
=
+^ h
k A
A V
1
in
0
0=
+^ h
Since, Vin is independent of k when seen from output mode, the
output voltage decreases with increase in k that leads to the decrease
of output impedance. Thus, input impedance increases and output
impedance decreases.
3.3 Option (B) is correct.
From the circuit, we have
Is I IZ L= +
or, IZ I Is L= 
(1)
Since, voltage across zener diode is 5 V so, current through 100W
resistor is obtained as
Is 0.05 A100
10 5=  =
Therefore, the load current is given by
IL R
5
L
=
Since, for proper operation, we must
have
IZ Iknes$
So, from Eq. (1), we write
0.05 A
R
5
L
 10 mA$
50 mA
R
5
L
 10 mA$
40 mA
R
5
L
$
40 10 3#

R
5
L
$
1
40 10 3#

R
5
L#
40 10
5
3
#
 RL#
or, 125W RL#
Therefore, minimum value of 125RL W=
Now, we know that power rating of Zener diode is given by
PR V I maxZ Z= ^ h
I maxZ^ h is maximum current through zener diode in reverse bias.
Maximum currrent through zener diode flows when load current is
zero. i.e.,
I maxZ^ h .I 100
10 5 0 05s= =
 =
Therefore, PR 5 0.05 W#=
250 mW=
3.4 Option (A) is correct.
For the given circuit, we obtain the small signal model as shown in
figure below :
We obtain the node voltage at V1 as
R
V
R
sC
V g V1D
L
m i
1 1+
+
+ 0=
& V1
R R
sC
g V
1
1
1
D
L
m i=
+
+

Therefore, the output voltage V0 is obtained as
V0
R
sC
V R
1
L
L1=
+
R
sC
R
R R
sC
g V
1 1
1
1
L
L
D
L
m i=
+ +
+
J
L
K
K
K
N
P
O
O
O
so, the transfer function is
V
V
i
0
sC R R
R R sCg
1 D L
D L m=
+ +

^ h
Then, we have the pole at
C R R
1
D L
w =
+^ h
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NO
DIA
ww
w.n
odi
a.c
o.in
The equivalent circuit of given amplifier circuit (when CE is
connected, RE is shortcircuited)
Input impedance Ri R rB= p
Voltage gain AV g Rm C=
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance Rin  [ ( )]R r R1B Eb= + +p
Input impedance increases
Voltage gain AV g R
g R
1 m E
m C= + Voltage gain decreases.
3.138 Option (A) is correct.
In common emitter stage input impedance is high, so in cascaded
amplifier common emitter stage is followed by common base stage.
3.139 Option (C) is correct.
We know that collectemitter break down voltage is less than
compare to collector base breakdown voltage.
BVCEO BV< CBO
both avalanche and zener break down. Voltage are higher than
BVCEO.So BVCEO limits the power supply.
3.140 Option (C) is correct.
If we assume consider the diode in reverse bias then Vn should be
greater than VP .
V V<P n
by calculating
VP 4 5 Volt4 4
10
#= + =
Vn 2 1 2 Volt#= =
here V V>P n (so diode cannot be in reverse bias mode).
apply node equation at node a
V V V
4
10
4 1
a a a + + 2=
V6 10a 8=
Va 3 Volt=
so current Ib 4
0 3
4
10 3=  + 
Ib 1 amp4
10 6=  =
3.141 Option (D) is correct.
By applying node equation at terminal (2) and (3) of OP amp
V Q V V
5 10
a a 0 +  0=
V V V2 4a a 0 +  0=
V0 V3 4a= 
V V V100 10
0a a0 +  0=
V V V10a a0 + 0=
V11 a V0=
Va
V
11
0=
So V0
V
11
3 40= 
V11
8 0 4=
V0 5.5 Volts=
3.142 Option (B) is correct.
Circuit with diode forward resistance looks
So the DC current will
IDC ( )R R
V
f L
m
p
=
+
3.143 Option (D) is correct.
For the positive half cycle of input diode D1 will conduct & D2 will
be off. In negative half cycle of input D1 will be off & D2 conduct so
output voltage wave from across resistor (10 )kW is –
Ammeter will read rms value of current
so Irms ( )half wave rectifierR
Vm
p=
(10 )k
4
pW
= .0 4p= mA
3.144 Option (D) is correct.
In given circuit positive feedback is applied in the opamp., so it
works as a Schmitt trigger.
Page 33
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NO
DIA
ww
w.n
odi
a.c
o.in
3.145 Option (D) is correct.
Gain with out feedback factor is given by
V0 kVi=
after connecting feedback impedance Z
given input impedance is very large, so after connecting Z we have
Ii Z
V Vi 0=  V kVi0 =
Ii Z
V kVi i= 
input impedance Zin ( )I
V
k
Z
1i
i= =

3.146 Option (A) is correct.
3.147 Option (A) is correct.
For the circuit, In balanced condition It will oscillated at a frequency
w
.
10 / secrad
LC
1
10 10 01 10
1
3 6
5
# # #
= = =
 
In this condition
R
R
2
1
R
R
4
3=
5100
R
1=
R 20 k 2 104#W W= =
3.148 Option (C) is correct.
V0 kept constant at V0 6 volt=
so current in 50W resistor
I
50
9 6
W
= 
I 60 m amp=
Maximum allowed power dissipation in zener
PZ 300 mW=
Maximum current allowed in zener
PZ ( )V I 300 10maxZ Z
3
#= = 
& ( )I6 300 10maxZ
3
#= = 
& ( ) 50 m ampI maxZ= =
Given knee current or minimum current in zener
( )I minZ 5 m amp=
In given circuit I I IZ L= +
IL I IZ= 
( )I minL ( )I I maxZ= 
(60 50)m amp m amp10=  =
( )I maxL ( )I I minZ= 
(60 5) 55 m amp=  =