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Page 4

Implementation:



(A) RTL Description(VHDL Code):

To read data from ADC
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity AD1 is
Port (
--General usage
CLK : in std_logic;
RST : in std_logic;

--Pmod interface signals
SDATA1 : in std_logic;
SCLK : out std_logic;
nCS : out std_logic;

--User interface signals
DATA1 : out std_logic_vector(11 downto 0);
START : in std_logic;
DONE : out std_logic
);

end AD1 ;

architecture AD1 of AD1 is

type states is (Idle,
ShiftIn,
SyncData);
signal current_state : states;
signal next_state : states;
signal clk_div:std_logic;
signal temp1 : std_logic_vector(15
downto 0);
shared variable clk_div1: std_logic:='0';
signal clk_counter : std_logic_vector(1
downto 0);
signal shiftCounter : std_logic_vector(3
downto 0) := x"0";
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
shared variable count:std_logic_vector(1 downto
0):="00";


begin


clock_divide : process(rst,clk)
begin
if rst = '1' then
clk_counter <= "00";
elsif (clk = '1' and clk'event) then
count:=count+1;
if (count="11") then
clk_div1:=not clk_div1;
count:="00";
end if;
end if;
clk_div<=clk_div1;
end process;

SCLK <= not clk_div;


counter : process(clk_div, enParalelLoad,
enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then

if (enShiftCounter = '1') then
temp1 <= temp1(14 downto 0) &
SDATA1;

shiftCounter <= shiftCounter + '1';
elsif (enParalelLoad = '1') then
shiftCounter <= "0000";
DATA1 <= temp1(11 downto 0);

end if;
end if;
end process;

---------------------------------------------------------------------
------------
--
SYNC_PROC: process (clk_div, rst)
begin
if (clk_div'event and clk_div = '1') then
if (rst = '1') then
current_state <= Idle;
else
current_state <= next_state;
end if;
end if;
end process;

OUTPUT_DECODE: process (current_state)
begin

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if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nCS <='1';
enParalelLoad <= '0';
elsif current_state = ShiftIn then
enShiftCounter <='1';
DONE <='0';
nCS <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then
enShiftCounter <='0';
DONE <='0';
nCS <='1';
enParalelLoad <= '1';

end if;
end process;

NEXT_STATE_DECODE: process (current_state,
START, shiftCounter)
begin

next_state <= current_state; -- default is to stay
in current state

case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftIn;
end if;
when ShiftIn =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;

end AD1;

12 bit binary to 7 segment display

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.numeric_std.all;


entity BCD12SEVSEG is
Port ( u_data:in std_logic_vector(7 downto
0);d_in : in STD_LOGIC_VECTOR (11 downto
0);clk,done: in std_logic;
d_o : out STD_LOGIC_VECTOR (10 downto
0),control:out std_logic);
end BCD12SEVSEG;
architecture Behavioral of BCD12SEVSEG is

signal temp: std_logic_vector(11 downto
0):="000000000000";
signal temp1: std_logic_vector(15 downto
0):="0000000000000000";
signal shcntr: integer:=0;
signal i1,i2,i3,i4: std_logic_vector(3 downto 0);
signal state: integer range 0 to 5;
shared variable d_out1,d_out2,d_out3,d_out4:
std_logic_vector(10 downto 0);
shared variable c:std_logic_vector(1 downto
0):="00";
shared variable cld: integer:=0;
signal clk_t:std_logic;
shared variable clkt: std_logic:='0';
begin
--
process
begin
wait until rising_edge(clk);

case state is

when 0 =>
if(done='1') then
temp<=d_in;
shcntr<=0;
temp1<=(others =>'0');
state<=1;
end if;


when 1 => if shcntr/=12 then
temp1<=temp1(14 downto 0) & temp(11);
temp<=temp(10 downto 0) & '0';
shcntr<=shcntr+1;
state<=2;
end if;

when 2=> if shcntr<12 then
if temp1(3 downto 0)>="0101" then